Mark C. DiVecchio, BSEE, MSCS, PE

Silogic Systems
9888 Carroll Center Road, Suite 102
San Diego, CA 92126
(858) 566-6810

PROFESSIONAL SPECIALTY

EDUCATION

Moore School of Electrical Engineering at the University of Pennsylvania
Philadelphia, PA
MS in Computer and Information Sciences 1978

Carnegie Institute of Technology at Carnegie-Mellon University
Pittsburgh, PA
BSEE (Computer Emphasis) 1970

BUSINESS EXPERIENCE

ENTREPRENEUR

• Owner of the VLSI design company Silogic Systems and the software development company Athena Systems Development Group.
• VLSI design for a Huntsville based manufacturer of high performance graphics workstations.
• Developed and continue to enhance a C++ program used by a major computer monitor manufacturer to perform CRT color adjustment.
• X-Windows graphics programming for a clip-art based drawing package.
• Unix System Administrator for a heterogeneous network consisting of IBM, Sony, HP and Sun workstations.
• VLSI design for a San Diego streaming tape company.
• Implemented a XENIX based store and forward message switch for 80286 based microcomputers.
• Developed a terminal emulator (run on an IBM PC) for the Digital Equipment Corporation VT100 and VT102 Video Terminals and for Tektronix 4014 Graphics Terminals. Currently marketing that program to the data processing community.

1985 ENCORE COMPUTER CORPORATION

1983-1984 MEGATEK CORPORATION, SAN DIEGO, CA.

Manager of the Hardware Development group within the Advanced Development Department. Managed a team of eleven Engineers designing and debugging Megatek's next generation graphics processor. Scheduled and coordinated the transfer of the final design into production.

1978-1983 NATIONAL ADVANCED SYSTEMS, SAN DIEGO, CA.

Section Head of the Logic Design group which developed medium-scale IBM 370/4341 plug-compatible mainframe processors. Planned and scheduled the manpower and financial resources for this group of 25 engineers with a budget of between 1 and 2 million dollars per year. Developed procedures for the use of the Computer Aided Design System and the ECL design rules used by the engineers.

Technical

Designed and debugged the floating point processor attachment for the NAS products. Participated in the design and verification of a system using the industry's first ECL Gate Arrays. Responsible for the technical integration of the complete mainframe.

1973-1978 BURROUGHS CORPORATION, PAOLI, PA.

Logic design manager on a program to develop a large high-speed ECL radar processor. Responsibilities included scheduling the logic design and checkout of that 30,000 IC mainframe.

Technical

Designed the floating point processing element for the Parallel Element Processing Ensemble (PEPE). The design included a 32 bit processor and a micro-programmed control unit. Task leader of the debug team as well as responsible for debugging the Floating Point processor. Published one paper on the design of a portion of PEPE and hold two patents on that design.

1970-1973 U.S. ARMY, FORT BELVOIR, VA.

ADDITIONAL INFORMATION

Amateur Radio Operator K3FWT, Private pilot, bicyclist and skier. Member IEEE Computer Society, the ACM, and the Computer Consultants of San Diego (CCSD).